Campaign openReview workflow: community reviewRecognition onlyRecognition rule: community vote IEEE Honors

Complete Reversible Computation

Explore reversible computing architectures that reduce dissipation while accounting for speed, error correction and information erasure.

Directive & Constraints

Model reversible Toffoli or Fredkin gates, including initialization, error correction and reset costs. State temperature, clock speed and error rate, and distinguish reversible logic from Landauer-limited information erasure.

Take on this Campaign

Open a research workspace to reason with Vera and prepare evidence for this campaign's Ledger.